This disclosure relates generally to electronic devices, and in particular but not exclusively, relates to circuitry that provides linear on-die termination for a bus, such as a bus in an open-drain bus architecture system.
Operating frequencies of processors are progressively increasing. In order to take advantage of these high frequencies, computer systems attempt to transmit signals along their buses and between system components at comparable frequencies. The need for transmitting and receiving data between two system components (typically semiconductor components) at higher frequencies necessitates the design of faster input/output (I/O) circuits.
However, high-speed I/O circuits are often complex circuits. The complexity is partly due to the fact that such I/O circuits need to account for drive strength and degrading signal quality at high frequencies. Furthermore, the various components of these I/O circuits often have non-linear current-voltage (I-V) characteristics, which make prediction of drive strength difficult in noisy environments, and thus necessitate complex designs for these I/O circuits in order to compensate for the non-linear I-V characteristics. The complexity in design causes increased consumption of real estate on an integrated chip, which translates directly into increased manufacturing costs and increased time-to-market for the particular product.
Proper termination is also an issue with these high-speed I/O circuits. When transmitting and receiving data at high frequencies between system components, some problems are encountered. Buses behave like transmission lines, where impedance mismatches lead to signal reflection and interference effects, such as ring-backs and overshoots. Maintaining signal quality over interconnections thus typically require termination of the transmission lines (e.g., buses) with matching impedances to minimize signal reflections.
With what is sometimes referred to as xe2x80x9cdual-ended termination,xe2x80x9d transmission lines used to carry signals in both directions are terminated at both ends (e.g., at agents at each end), such that a terminating resistor matches a characteristic impedance of the transmission line. However, having the termination resistor at the driving end of the transmission line needlessly dissipates power, particularly when a low voltage level (e.g., a binary 0) is driven onto the transmission line, since a current flows through the termination resistor at that driving end. Attempts to avoid this power dissipation include system architectures that provide a termination resistor on only one side of the transmission line (sometimes referred to as xe2x80x9csingle-ended terminationxe2x80x9d), but such single-ended termination architectures result in a positive reflection coefficient at the un-terminated end of the transmission line, which is an adverse result for a high-performance and high frequency bus. Furthermore, the various configurations that are currently used to provide the terminating resistor(s) also suffer from complexity and waste of valuable real estate on the chip.